1. Field of the Invention
This invention relates to accessing dynamic random access memories (DRAMS) and more particularly to modifying a row address strobe (RAS) for DRAMs based on the existence of waits states.
2. Description of the Related Art
DRAMs require a minimum amount of time (RAS precharge time) between active row address strobes. Referring to FIG. 1, that minimum time period 110 occurs where RAS is inactive (high). The time period is required because once RAS transitions to inactive, it must remain inactive for the minimum time shown at 110 to precharge the internal circuitry in the DRAM for the next active cycle. The RAS high time or precharge time varies according to the access speed of the DRAM. For example, a DRAM with 50 nanosecond access time can have a 30 ns RAS precharge time. A 60 ns DRAM can have a 35 ns precharge time and a DRAM with 70 ns access times can have a precharge time of 40 ns. Note that the use of the term "RAS" rather than "RAS" is for convenience and is not intended to suggest the active state of the signal.
When DRAM controllers control DRAMs with different access speeds, the DRAM controller must account for the different DRAM timing requirements. One such timing requirement, besides the RAS precharge requirement is the RAS pulse width shown in FIG. 1 as time period 120. In order to account for slower DRAMs, it is known to insert wait states in the DRAM access cycle so that the RAS and CAS strobes are extended. However, inserting wait states to extend the RAS active strobe does not solve the problem of having different RAS precharge (inactive or high time) requirements for DRAMs with different access speeds.